(1) Field of the Invention
The invention relates to dynamic memory data flow, and more particularly, to a data flow scheme for a high speed DRAM that selectively precharges the data line and data line bar signals of selected cells to improve the read and write speeds.
(2) Description of the Prior Art
Dynamic memory, of DRAM, devices are used in a variety of applications, such as personal computers. DRAM devices offer a low cost, high memory capacity alternative to static or SRAM devices. However, with the advent of microprocessors capable of operation in excess of 1 gigahertz, the access speed of the DRAM can become an operational bottleneck for the system. To improve the performance of the DRAM, double date rate (DDR) devices have been developed wherein data may be accessed using both the rising and falling edges of the system clock.
Referring now to FIG. 1, a part of a prior art DRAM memory device is shown. A single DRAM bit cell 6 is shown as the storage capacitor CCELL 24 and the access transistor NC 23. The memory state of the bit cell 6 depends on the charge stored on CCELL 24. A bit line (BL) sense amplifier 4 is shown. The BL sense amplifier 4 comprises a pair of cross-coupled inverters 10 and 14 that are coupled between the BL and BLB nodes. The BL node is coupled to the drain of the word line access transistor NC 23 for the bit cell 6. Bit select (BS) transistors N1 18 and N2 22 are used to selectively couple the BL and BLB nodes to the data line (DL) and DLB nodes. A write driver 25 and a data line amplifier 26 are further coupled to the DL and DLB lines. While only a single bit cell 6 is shown it is understood that a useful DRAM memory device would comprise a plurality of such memory cells 6 and BL sense amplifiers 4 are arranged in an addressable array.
Referring now to FIG. 2, a prior art timing diagram demonstrates the signal performance of the prior art device. The device clock is shown as CLK. In the diagram, the device begins in the ACCESS STATE of STANDBY or ACTIVE. During the STANDBY state, the WL is not asserted. Therefore, the bit cell 6 is not selected and the stored charge is retained in CCELL 24. Further, the BL and BLB signals are pre-charged to about ½ the VCC voltage of the circuit. This pre-charge operation is called a ROW PRECHARGE and is performed so that the BL and BLB nodes are in a preferred condition for a read operation.
The DL and DLB nodes are pre-charged to about VCC during this STANDBY state. This pre-charge operation is called a COLUMN PRECHARGE. The COLUMN PRECHARGE STATE is shown on the diagram. During the STANDBY state, the COLUMN PRECHARGE STATE is ON.
The DRAM device transitions to the WRITE state due to an external access command. In response to the WRITE state transition, the WL for a selected bit cell is asserted. Note that the DRAM device selects a particular group of bit cells, such as a byte or word, based on the address given by the external writing device. The assertion of WL causes the bit cell access transistor NC 23 to turn ON. With NC 23 ON, the charge on CCELL 24 is shared onto the BL node. The BL and BLB signals voltages will deflect from the ½ VCC value to reflect this charge sharing. The BL sense amplifier 4 amplifies the voltage difference between BL and BLB to cause BL and BLB signals to be driven to a larger differential value.
The bit select (BS0) signal for the first column is asserted 34 to couple DL to BL and DLB to BLB. As an important observation, note that both the DL and DLB signals are in the COLUMN PRECHARGE STATE of VCC prior to the assertion of BS0. In the prior art, the COLUMN PRECHARGE is synchronized to the bit select signal. Once the PRECHARGE is turned OFF 36, the WR DRIVER 25 forces a differential voltage on DL and DLB corresponding to the data state that is being written to the cell 6. In this case, the DL signal is forced low 38 while DLB is held at VCC such that a low state (VSS) can be written into the cell 6.
A potential problem in the operating design is shown when the DL signal exhibits a slow transition 38 from high to low due to excessive RC loading of the DL signal. In some DRAM designs, the DL or DLB lines have very long conductive line routings of, for example, 4000 microns. The RC loading represented by these long routings can slow the DL and DLB switching significantly. Further, note that the DL signal delay causes the BL0 and BL0B signal switching to be delayed. In the worst case, the BL0/BL0B signals may be delayed beyond the available BS0 window. The result is a MISSED BIT WRITE by the BL sense amplifier. If the DRAM is operated at a high speed, data errors will result from the operating design of the prior art device. After the write of the second byte (BS1), the COLUMN PRECHARGE STATE returns to the ON state 42. Once again, the PRECHARGE STATE is synchronized to the bit select signals (BS0 and BS1).
The DRAM device now transitions to a READ state. Note that COLUMN PRECHARGE STATE continues to be ON until the first data read operation 44. The READ operation begins with an external read access to the DRAM device. BS0 is asserted to cause the BL and BLB charge sharing and BL sense amplification to occur as described above. When the BS0 is enabled for this column, DL is again coupled to BL and DLB is again coupled to BLB. The sense amplifier 4 drives the DL and DLB lines with the differential voltage as shown. After the READ operation, the device returns to the STANDBY state, and the WL row is deactivated 46.
Several prior art inventions describe high speed DRAM methods and circuits. U.S. Pat. No. 6,154,418 to Li discloses a writing scheme for a double data rate (DDR) synchronous DRAM (SDRAM). The memory bank is divided into two planes. U.S. Pat. No. 6,215,710 to Han et al describes a method for controlling a data strobe signal for a DDR SDRAM. U.S. Pat. No. 6,229,757 to Nagata et al describes a data strobe method and a circuit for a DDR SDRAM.